Electro-Thermal Modeling of LDMOSFETs for Power-Amplifier Design

Abstract—A new approach for the electro-thermal modeling of LDMOSFETs for power-amplifier design that bypasses pulsed-IVs and pulsed-RF measurements is presented in this paper. The existence of low-frequency dispersion in LDMOSFETs is demonstrated by comparing pulsed IVs with iso-thermal IVs.

The modeling technique uses iso-thermal IV and microwave mea- surements to obtain the temperature dependence of small-signal parameters. Optimized tensor-product B-splines, which dis-tribute knots to minimize fitting errors, are used to represent thesmall-signal parameters and extract the large-signal model as a function of voltages and temperature. The model is implemented on ADS and is verified by simulating and measuring the power harmonics and IMD large-signal performance of a power ampli- fier. The impact on the model of temperature-dependent drain and gate charge is investigated. The presented model is found to compare well and, in some cases, exceed the existing MET model for LDMOSFETs.

Index Terms—B-spline representation, electrothermal FET model, LDMOSFET, nonquasi static equivalent circuit, RF power amplifiers.

I. INTRODUCTION

PACKAGED silicon power LDMOSFETs are finding in-creasing use for linear RF power amplification. Such de-vices are now unseating traditional heterojunction bipolar tran-sistors (HBTs) and high electron-mobility transistors (HEMTs) at frequencies up to 2.3 GHz for cellular base stations and high- power transmitters [1], [2]. The increasing use of these devices calls for better models targeted toward RF power-amplifier de- sign [3]. Collantes et al. [4] recently proposed a nonelectro- thermal pulsed-IV measurement-based table model using ap-proximation B-splines. Pulsed IVs have been used extensively for modeling of devices that suffer from low-frequency disper-sion, either due to thermal, trapping, or parasitic bipolar effects [5]. However, because of the fact that pulsed IVs depend upon the original bias point used to generate them, there are an in- finite number of different pulsed-IVs characteristics possible.
B-splines and their tensor representation have also been used extensively in modeling of FETs [6]–[8]. Motorola's electro-thermal model (MET) [9], a variant of the Curtice model [10], uses cold-biased pulsed IVs and cor-responding pulsed-RF measurements to extract a full electro- thermal model of the LDMOSFET. However, most microwave laboratories unfortunately do not possess such expensive equip- ment and, hence, need to use other approaches to acquire iso- thermal data for extracting device models for power devices.
This paper presents an alternative approach that uses iso-thermal IVs and microwave measurements to extract a full electro-thermal model of LDMOSFETs. It begins by explaining the iso-thermal IV measurement technique and comparing iso-thermal IVs with pulsed IVs. The temperature dependence of small-signals parameters is demonstrated. Three-dimensional (3-D) tensor product B-splines (TPSs) are used to represent small-signal parameters as a function of drain–source and gate–source voltages and average device temperature, and are used to extract large-signal parameters.
The developed model is implemented in the ADS circuit simulator and used for power-amplifier simulations. Performance matrices predicted in ADS, such as power harmonics and intermodulation distortion (IMD), are compared with measured results to verify the modeling approach.

II. DC, ISO-THERMAL, AND PULSED IVS

For this entire study, we have used Motorola's MRF 181 RF power -channel-enhancement-mode lateral diffusedMOSFET [11]. The MRF 181 has a total gatewidth of 20.16 mm, a gate length of 1.5 m, and a maximum junction to case thermal resistance of 5.42 C/W.
A normal dc current–voltage–temperature (IVT) of a device is measured by setting the substrate temperature and gatesource and drain–source voltages and by mea suring the drain current and the average surface device temperature using an infrared thermometer. Fig. 1 shows the measured dc IVT for a of 35 C and a range from 4 to 6.5 V in steps of 0.25 V. The device temperature is superimposed on the curve.Using a least-squares fit on themeasured device-temperature versus intrinsic-device power characteristics for all bias points (see Fig. 2), we can extract the thermal resis- tance in the electro-thermal model proposed in Fig. 3 [12].

Fig. 1. Measured IV, with T superimposed, for a constant substrate
temperature of 35 C.


Fig. 2. Prediction of device temperature (solid lines) compared with measured
values (circles) using a single Rth for a given Tsub of 35 C.

Fig. 3. (A) Intrinsic self-biasing model topology to fit both dc and RF.
(B) Electrical network representing the thermal network model for the thermal
boundary conditions used.

Using this Rh value, the device temperature for a given bias can then be computed. The solid lines in Fig. 2 show the predicted Tdev for a Tsub of 35 C, while the circles give the measured . A single Rth value does an excellent job in mapping the entire device average thermal response at dc. The curves given in Fig. 1 yield on differentiation the effective dc conductance (gd,dc) and transconductance (gm,DC), which will differ fromthe ac conductance (gd,RF) and transconductance (gm,RF) due to low-frequency dispersion effects. Such dispersion can be caused by either thermal and/or parasitic effects. While III–V and silicon on insulator (SOI) devices suffer from both these effects, it is generally thought that thermal effects are the major contributor to low-frequency dispersion in LDMOSFETs. The p+ sinker diffusion kills the floating base bipolar and, hence, dispersion fromthis and similarmechanisms are not expected.
An approach to verify this would be to measure IVs that isolate the two major contributors to dispersion. Pulsed IV measurements are iso-thermal in nature, bypassing both of these dispersion effects and can be used as one measure. On the other hand, a measurement scheme that bypasses only thermal effects will yield a true iso-thermal IV.

From Figs. 4 and 5, it can be observed that the iso-thermal IVs are in good agreement with the hot-biased pulsed IVs. For 75 C, the hot- and cold-biased pulsed IVs are in agreement at mid drain currents (0.2 A), but can depart significantly at high

Fig. 4. Comparison between iso-thermal IV (solid lines), cold pulsed IVs
(dashed lines), and hot-biased pulsed IVs (dashed–dotted line) for Tdev of
75 C. * denotes the bias point used for hot-biased pulsed IVs. V ranges from
4 to 6.5 V in steps of 0.5 V. / denotes V = 4 V, denotes Vgs =4:5 V,
denotes Vgs =5 V, . denotes Vgs =5:5 V, denotes Vgs =5:5 V, and
denotes Vgs =6 V.

Fig. 5. Comparison between iso-thermal IV (solid lines), cold pulsed IV (dashed lines) and hot-biased pulsed IV (dashed–dotted line) for T of 105 C. * denotes the bias point used for hot-biased pulsed IVs. V ranges from 4 to 6.5 Vgs in steps of 0.5 Vgs. / denotes V =4 V, denotes Vgs =4:5 V, denotes Vgs =5 V, . denotes Vgs =5:5 Vgs, denotes Vgs =5:5 V, and denotes V =6 V.
and somewhat at low currents. This trend is also observed for similar measurements at higher and lower temperatures. However, for similar curves measured at 45 C, the hot- and cold-biased pulsed IVs were found to agree well.
It is safe to conclude that the LDMOSFET does indeed suffer from some dispersion effects, which clearly become more profound at higher device temperatures (corresponding to biasing the device at higher drain currents). This dispersion, however, is not as profound as that suffered by III–V devices or floating-body SOI devices, due to the presence of the psinker body tie in LDMOSFETs.
Given the fact that there can be much variation among coldand hot-biased pulsed IVs, which are functions of their starting

Fig. 6. Trajectories of R (solid lines) and R (dashed lines) as a function of R for a constant I .

bias point, and that for a wide range of temperature, the iso-
thermal IVs agree well with the hot-biased pulsed IVs, the iso-
thermal IVs can be used as an alternative data source to pulsed
IVs.

III. TEMPERATURE-DEPENDENT SMALL-SIGNAL PARAMETERS

The iso-thermal IV measurement tool can also be used to acquire iso-thermal -parameters. By using this scheme, iso-thermal microwave data was acquired at temperatures ranging from45 C to 105 C in steps of 15 C.Athru-reflect line (TRL) was used to obtain calibrated data at the gate and drain planes.
The -parameters of the intrinsic small-signal topology [18], [12] can be written as , where and are the bias-dependent capacitance (trans-capacitance), conductance (transconductance), and nonquasi- static (NQS) times constants, respectively. Note that , and . A two approximation can be made such.
The microwave data is deembedded using the NQS multibias approach given in [14] and [15] to extract small-signal param- eters and device parasitics. This involves fitting the extrinsic -parameters and then using analytical expressions for intrinsic
and extrinsic parameters that are functions of -parameter fitting constants. These expressions indicate a continuum of solutions as a function of , the source parasitic resistance. A multibias analysis is used to plot the and trajectories as a function of for different bias points for the same drain current as shown in Fig. 6. The intersection point gives the value. The bias resistances are found to increase slightly with increasing drain current. Due to the relatively small values of the parasitics, their possible temperature dependence has been neglected. Fig. 7 shows that the resulting -parameter fits at V and V and of 90 C. The small-signal model does an excellent job in fitting the device microwave pa-rameters.

Figs. 8 and 9 show the variation in the raw extracted and as a function of device temperature over all measured bias points. Note that the extrinsic values plotted are a bit

Fig. 7. Comparison between fitted S-parameters (solid lines) and measured

data (plus signs) for Vgs = 5:5 V;Vgs =15 V; and T of 90 C.

Fig. 8. Extracted g for V =4 Vto 6:5 V in steps of 0.5 V for different
T : T =105 C (solid lines), T =90 C (dashed lines), T =
75 C (dashed–dotted lines), T =60 C (dotted lines), and T =45 C
(plus signs).

skewed as a result of the parasitic present in the dc-biasing net- work. is from 4 to 6.5 V in steps of 0.5 V. Solid lines are for a of 105 C, dashed lines are a of 90 C, dashed–dotted lines are for a of 75 C, dotted lines are for a of 60 C, and plus signs are for a of 45 C, re- spectively.

It can be seen from Figs. 8 and 9 that while is relatively temperature independent, is quite sensitive to temperature.

Fig. 10. Extracted C for V =4 Vto 6:5 V in steps of 0.5 V for different
T : T = 105 C (solid lines), T =90 C (dashed lines), T =
75 C (dashed–dotted lines), T =60 C (dotted lines), and T =45 C
(plus signs).

Due to the cooling limitation of the substrate temperature controller used, microwave small-signal data is unavailable at high gate and drain voltages. Ideally, a pulsed dc and pulsed RF technique can be used to access this region without cooling the substrate. However, in the absence of such pulsed RF equip- ment for high-power transistors, an extrapolation scheme has been used to obtain data in this region.

IV. LARGE-SIGNAL MODELING

The large-signal electro-thermal model for the LDMOSFET shown in Fig. 3 features a simple thermal network topology, which calculates the steady state iso-thermal temperature of the LDMOSFET as a function of the power dissipated by the LD- MOSFET. The model includes a parasitic bipolar driven by the impact ionization current so as to model low-frequency disper- sion [12]. The large-signal representations can be obtained from the extracted small-signal model parameters using path-inde-pendent integration performed in this paper with tensor-product

B-splines (one possible integration path is shown for the sake of clarity) as follows:



where and are the pulsed-IV voltages at which the pulsed-IV current and charges are predicted (see [12]) for a dc-bias point of and . Note that following our discus-sion in Section II, the dc-bias dependence of the pulsed IV and charges can be neglected in the LDMOSFET. The extracted small-signal parameters are fitted using a knot optimized 3-D TPSs technique [16]. In this optimized knot placement technique, an error function is computed to determine how close a fit it is to the original data. The knot placement is then readjusted so that the knot concentration in the higher error region is increased, while reducing the concentration in the lower error region. Note that the overall number of knots in a particular bias direction are kept the same.
It is only the knot distribution that is changed. This technique is necessary in light of the steep knee in the intrinsic device drain current. Nonoptimized TPSs are unable to handle these regions and give rise to oscillatory behavior.

IV. CONCLUSION

We have presented a technique using iso-thermal IVs for the electro-thermal modeling of LDMOSFETs that bypasses the use of pulsed IVs and pulsed RF measurements. Iso-thermal IVs have been compared with hot- and cold-biased pulsed IVs demonstrating that there is indeed some low-frequency dispersion in LDMOSFETs. The technique using iso-thermal microwave measurements has been demonstrated for the extraction of temperature-dependent small-signal parameters. The conductance and capacitances C12 and C22 are found to be relatively temperature independent.
Knot optimized 3-D TPSs have been used to represent the drain current. Gate and drain charges are represented using the same TPS technique, but are modeled to be temperature independent. The electro-thermal model has been programmed in ADS and has been used to simulate a power amplifier. The model is able to do a very good job in predicting power har- monics and two-tone IMD power-amplifier performance. The model matches and, in some cases, exceeds the existing MET

Asignatura: CRF
Dujeiny J Sanchez Q
Extraido: ieeexplore.ieee.org/iel5/22/21710/01006418.pdf?arnumber=1006418